CD4013 Pinout
CD4013 Dual D Flip-Flop · Dual D-type flip-flop with set/reset, CMOS, supply 3–18V.
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q1 | Output | Flip-flop 1 output |
| 2 | /Q1 | Output | Flip-flop 1 inverted output |
| 3 | CLK1 | Control | Flip-flop 1 clock (rising edge) |
| 4 | RST1 | Control | Flip-flop 1 reset (active-high) |
| 5 | D1 | Input | Flip-flop 1 data input |
| 6 | SET1 | Control | Flip-flop 1 set (active-high) |
| 7 | VSS · GND | GND | Ground |
| 8 | SET2 | Control | Flip-flop 2 set (active-high) |
| 9 | D2 | Input | Flip-flop 2 data input |
| 10 | RST2 | Control | Flip-flop 2 reset (active-high) |
| 11 | CLK2 | Control | Flip-flop 2 clock (rising edge) |
| 12 | /Q2 | Output | Flip-flop 2 inverted output |
| 13 | Q2 | Output | Flip-flop 2 output |
| 14 | VDD | Power | Supply + (3–18V) |
How to read the CD4013 pinout
- 01
Find pin 1
One end of the chip has a half-circle notch or a dot; with the notch facing up, the top-left pin is pin 1.
- 02
Count counter-clockwise
Count counter-clockwise from pin 1: go down the left side first, then up the right side from the bottom.
- 03
Check the table below
Look up each pin's function by number in the table below; power/ground are color-coded, and alternate-function signals are in parentheses.
Frequently asked questions
Are SET and RESET active-high or active-low?
Active-HIGH on the CD4013 — a high level forces the output set/reset. This is opposite to the 74HC74, whose /PRE and /CLR are active-low. Tie unused SET/RESET pins to VSS.
How do I make a toggle (divide-by-2) flip-flop?
Wire /Q back to D. Each rising clock edge then toggles Q, dividing the clock frequency by 2 — handy for frequency dividers and debounced toggle buttons.
What happens if SET and RESET are both high?
Both Q and /Q go high — an invalid state. Avoid driving SET and RESET high at the same time.
Pinout data comes from TI CD4013B datasheet (standard DIP-14 numbering). Refer to the actual device datasheet as authoritative for the pinout.