Flip-Flop Simulator
Choose a flip-flop type, set inputs, clock it, and watch Q change in real time.
What it does: Interactively demonstrate D/JK/T/SR flip-flops: apply a clock and watch how Q changes.
When to use it: When learning sequential logic, memorizing characteristic tables, or understanding how counters/registers work.
D/JK/T are edge-triggered? ; SR is a set-reset latch.
MEANS —
No history yet. Each calculation is automatically saved to this device.
How to use the flip-flop simulator
Choose a type → set inputs → clock it and watch Q.
- 01
Choose a flip-flop type
D / JK / T are edge-triggered (update only on the clock rising edge); SR is a set-reset latch.
- 02
Set the inputs, then clock it
Click an input switch (e.g. J, K) to set 0/1, then press "Clock ↑" to generate a rising edge and watch how Q changes.
- 03
View the waveform and history
The timeline below records Q on each tick; to start over, click "Reset".
Characteristic table of the four flip-flops
Q is the present state, Q⁺ is the next state after the clock.
| Type | Inputs | Next state Q⁺ |
|---|---|---|
| D | D | Q⁺ = D |
| T | T | T=1 toggle / T=0 hold |
| JK | J K | 00 hold · 01 reset · 10 set · 11 toggle |
| SR | S R | 10 set · 01 reset · 00 hold · 11 invalid |
Standard digital-logic characteristic table (ideal edge-triggered).
Common questions, answered in 3 minutes
What is the difference between JK and SR?
For SR, S=R=1 is a forbidden state (output undefined), whereas JK defines that combination as "toggle", eliminating the invalid state, which is why JK is more commonly used.
What can a T flip-flop do?
When T=1 it toggles on every clock, equivalent to dividing the clock by two — it is the basic building block of counters/dividers.
Difference between "edge-triggered" and "level-triggered"?
Edge-triggered samples the input and updates only at the clock transition instant (e.g. the rising edge); level-triggered is transparent for the entire duration the clock is at a given level, which can cause race-through. This tool models an ideal rising edge.
Why did Q not change when I changed the input?
An edge-triggered flip-flop updates only on the clock rising edge. After changing the input, click "Clock ↑" again.
Why is the D flip-flop called "data/delay"?
It copies the input D unchanged to output Q on the next clock edge, effectively delaying the data by one clock period; it is the basic building block of a register.
Standards and sources referenced by this tool
| Item | Value / Formula | Source |
|---|---|---|
| Characteristic equation | D/T/JK/SR | Digital logic standard |
| Triggering | Rising edge (ideal) | edge-triggered model |
Ideal edge-triggered model, no propagation delay/metastability, no external API.