74HC Logic Gates: Pinout Cheat-Sheet and Truth Tables for the 00, 02, 04, 08, 32 and 86

Gate comparison table

All six parts are DIP-14 with pin 7 = GND and pin 14 = VCC. The column that matters is the last one — what sits on pin 1. On every quad gate except the NOR, pin 1 is an input (1A). On the 74HC02 NOR it is the output (1Y):

⚠️ Headline takeaway: 74HC00 / 08 / 32 / 86 are pin-for-pin identical (input-first), the 74HC04 is the hex-inverter layout, and the 74HC02 NOR is output-first — pin 1 is 1Y. Swapping a NOR into a NAND footprint puts your inputs on the output pins. Confirm against the 74HC00 and 74HC02 pinout pages before wiring.

Quad gate pinout: 74HC00 / 74HC08 / 74HC32 / 74HC86

The quad NAND (74HC00), quad AND (74HC08), quad OR (74HC32) and quad XOR (74HC86) all use the same DIP-14 map: four gates, each with two inputs (A, B) and one output (Y). Only the logic function inside changes — the pins do not:

So gate 1 is pins 1–2 (in) and 3 (out); gate 2 is pins 4–5 (in) and 6 (out); gate 3 is pins 9–10 (in) and 8 (out); gate 4 is pins 12–13 (in) and 11 (out). Memorise this one map and you have four parts.

74HC04 hex inverter pinout

The 74HC04 is a hex inverter — six NOT gates, each with a single input and a single output. Single-input gates need fewer pins, which is how six of them fit in the same DIP-14:

Each inverter is a simple input → output pair (1A→1Y, 2A→2Y, … 6A→6Y), so the inputs and outputs alternate down each side rather than grouping in pairs.

74HC02 NOR — the output-first trap

Here is the part that catches people out. The 74HC02 is a quad 2-input NOR, the same shape as the NAND on paper — but its pins are wired output-first. Pin 1 is the output 1Y, with the two inputs (1A, 1B) following on pins 2 and 3:

Compare pin 1: 1A on the NAND, 1Y on the NOR. This single non-obvious difference is the reason a NOR will not drop cleanly into a NAND layout — and the reason this cheat-sheet exists.

Truth tables

These are the logic functions each part implements (A, B → Y). Verify any of them — or build a multi-gate expression — with the Logic Gate Truth Table Generator, and simplify the resulting expression with the Boolean Algebra Simplifier.

AND (74HC08) and OR (74HC32)

NAND (74HC00) and NOR (74HC02)

NAND and NOR are simply the inverted AND and OR — the outputs above flipped:

XOR (74HC86)

XOR is HIGH only when the two inputs differ:

NOT (74HC04)

The inverter has a single input — output is the complement:

Never float a CMOS input

74HC is a CMOS family, and that brings one rule you must not break: never leave an input floating. An unconnected CMOS input is not a defined HIGH or LOW — it drifts with nearby noise and can park the gate in its linear region, where it draws excess supply current and the output oscillates or behaves erratically. Tie every unused input — including the inputs of gates you are not using in the package — either HIGH to VCC or LOW to GND, directly or through a pull resistor. This single habit eliminates a huge share of "intermittent" logic faults on the bench. What counts as a valid HIGH or LOW depends on the family thresholds — see the Logic Level Reference.

74HC vs 74HCT vs 74LS

The pinouts above are identical across 74HC and 74HCT — what changes is the input switching threshold:

• 74HC: true CMOS thresholds at roughly half of VCC. It expects clean, rail-to-rail logic swings on its inputs.
• 74HCT: TTL-compatible input thresholds (a valid HIGH as low as ~2V), so it can be driven reliably from 5V TTL or older logic whose HIGH output may not reach the full rail.

Rule of thumb: if a CMOS gate is fed from a 5V TTL output (or another HC part is fine and you are all-CMOS), HC is okay; if you must accept marginal TTL-level HIGHs, use the HCT variant. Check the actual voltage margins for your two parts with the Logic Level Reference before committing.

FAQ

Are all 74HC quad gates the same pinout?

No — and this is the single most useful thing to know on this page. The 74HC00 (NAND), 74HC08 (AND), 74HC32 (OR) and 74HC86 (XOR) really do share an identical input-first layout: pin 1 is input 1A, pin 3 is output 1Y, and so on around the package. But the 74HC02 (NOR) is the odd one out — it is wired output-first, so pin 1 is output 1Y, not an input. If you assume the NOR follows the same map as the NAND you will swap inputs and outputs on every gate. Cross-check each part against its datasheet, or verify the wiring against the Logic Gate Truth Table Generator.

Can I leave an unused 74HC input unconnected?

No. 74HC is CMOS, and a floating CMOS input is not a defined logic level — it drifts, picks up noise, and can sit in the linear region where the gate draws excess current and the output oscillates. Always tie every unused input either HIGH (to VCC) or LOW (to GND), directly or through a resistor, even on gates you are not using in the package. This is one of the most common causes of an "intermittent" logic circuit on the bench. The Logic Level Reference explains what counts as a valid HIGH or LOW.

What is the difference between 74HC and 74HCT?

The pinouts are identical; the difference is the input switching threshold. 74HC uses true CMOS thresholds at roughly half of VCC, so it expects clean rail-to-rail logic swings. 74HCT shifts its input thresholds to be TTL-compatible (a HIGH as low as about 2V), which lets it be driven reliably by 5V TTL or older logic families whose HIGH output may not reach the full rail. If you are interfacing a CMOS gate to a 5V TTL output, reach for the HCT variant or check the margins with the Logic Level Reference.

How many gates are in a 74HC04 vs a 74HC00?

The 74HC04 is a hex inverter: six independent NOT gates, each with one input and one output, packed into the DIP-14. The 74HC00 is a quad NAND: four gates, each with two inputs and one output. That is why the inverter can fit six gates in the same package — single-input gates take fewer pins. Both still use pin 7 for GND and pin 14 for VCC. See the /ic/74hc04 and /ic/74hc00 pinout pages for the per-pin maps.